An electronic computer aided design (“E-CAD”) package is utilized to construct a Very Large Scale Integration (“VLSI”) circuit design. The VLSI circuit design consists of a netlist that identifies electronic design elements (e.g., capacitors, transistors, resistors, etc.) and their interconnectivity (e.g., signal nets) within the VLSI circuit design. The VLSI circuit design is constructed from hierarchical cells (also known as design blocks) that provide specific functionality to the VLSI circuit design. Cells may be constructed from electronic design elements, nets and other cells, and may be re-used one or more times. Each use or instantiation of a cell in the VLSI circuit design is called an “instance.”
A signal net is a single electrical path in a circuit design that has the same electrical characteristics at all of its points. Any collection of wires that carries the same signal between design elements is a signal net. If the design elements allow the signal to pass through unaltered (as in the case of a terminal), then the signal net continues on subsequently connected wires. If, however, the design element modifies the signal (as in the case of a transistor or logic gate), then the signal net terminates at that design element and a new signal net begins on the other side.
A signal net may be divided into signal net ‘pieces’, each of which is part of a Highest Level Signal Name (“HLSN”). A HLSN is the unique signal name that identifies a collection of signal nets or ‘hierarchical signal net pieces’, which are the small pieces of intermediate wire (signal nets) in each hierarchical design block of a circuit design.
A significant characteristic of VLSI and other types of circuit design is a reliance on hierarchical description. A primary reason for using hierarchical description is to hide the vast amount of detail in a design. By reducing the distracting detail to a single object that is lower in the hierarchy, one can greatly simplify many E-CAD operations. For example, simulation, verification, design-rule checking, and layout constraints can all benefit from hierarchical representation, which makes them more computationally tractable. Since many circuit designs are too complicated to be easily considered in their totality, a complete circuit design is often viewed as a collection of design element aggregates that are further divided into sub-aggregates in a recursive and hierarchical manner. In VLSI circuit design, these aggregates are commonly referred to as design blocks or cells, as noted above. Each cell also typically has one or more ‘ports’; each port provides a connection point between a signal net within the cell and a signal net external to the cell.
A design engineer uses the E-CAD tool to analyze the VLSI circuit design during development. The E-CAD tool typically selects a ‘stage’ within the circuit design for analysis. The stage is contained within one cell that may be instantiated one or more times in the VLSI circuit design; the VLSI circuit design, therefore, may contain more than one identical stage. Each stage in the circuit design has instantiation-specific configuration information that is used by the E-CAD tool during analysis of the stage. The instantiation-specific configuration information may have several different sources, including input/output from other analysis tools and user input.
The E-CAD tool may perform several types of analyses (using different analysis tools, for example) on the VLSI circuit design, with each analysis utilizing particular configuration information. Each analysis tool that accesses configuration information typically parses textual configuration information contained in configuration files. These configuration files may therefore be parsed several times during analysis of the many stages of a VLSI circuit design.
If the VLSI circuit design contains billions of design elements and has many stages, the analyses can take hours or even days of processing time to complete, resulting in lost productivity. Continuous lost productivity due to lengthy engineering development slows technology advancement and can result in significant costs, as well as lost business.